The present invention relates generally to semiconductor chips and their fabrication and, more particularly, to analysis of semiconductor chips involving substrate removal.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip-packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or flip-chip packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is flipped over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as Ball Grid Array (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is single crystalline silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
Techniques have been developed to access the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. To acquire these images, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns. For example, on a die that is 725 microns thick, at least 625 microns of silicon is typically removed before IR microscopy can be used. Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished by first thinning the die across the whole die surface, often referred to as global thinning. Mechanical polishing, such as chemical-mechanical polishing (CMP), is one method for global thinning. Once an area is identified using IR microscopy as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques are often used to thin an area smaller than the die size.
During failure analysis, or for design debug, it is sometimes desirable to make electrical contact and probe certain circuit nodes on the circuit side or front side of a die, or to reconfigure the conductors in an integrated circuit. This access is generally done by milling through substrate to access the node, or milling to the node and subsequently depositing a metal to electrically access the node. Often, global and local thinning as described above are used to accomplish such milling.
Accurate determination of the thickness of the silicon in the back side, however, is not readily achieved, making the milling process difficult to control. When not controlled properly, substrate removal can result in damage to or destruction of circuitry and other substrate in the device. It is desirable to have the ability to determine the progression of the removal process including detecting the endpoint with sufficient accuracy to avoid such damage or destruction, which could often jeopardize further device analysis.
The present invention is directed to a method and system for analyzing a semiconductor chip having silicon-on-insulator (SOI) structure and a back side opposite a circuit side. The chip analysis includes controllably removing substrate from the chip, and is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, substrate is removed from a semiconductor chip having silicon-on-insulator (SOI) structure and a back side opposite circuitry near a circuit side. A portion of substrate in the back side of the semiconductor chip is removed as a function of a detected selected substrate material that is sputtered from a region of the substrate.
According to another example embodiment of the present invention, substrate is removed from a semiconductor chip having SOI structure and a back side opposite a circuit side. An ion beam is directed at a portion of substrate in the back side of the chip and ions are sputtered from the substrate, thereby removing substrate and forming an aperture in the back side. The concentration of sputtered ions is detected and, in response to the concentration of the detected sputtered ions reaching a threshold level, the substrate removal rate is adjusted. When the concentration of the detected sputtered ions reaches a threshold level corresponding to reaching an endpoint of the substrate removal process, the removal process is terminated.
According to another example embodiment of the present invention, a system is arranged for removing substrate from a semiconductor chip having silicon-on-insulator (SOI) structure and a back side opposite a circuit side. A substrate removal arrangement is adapted to remove substrate from and form an aperture in the back side of the semiconductor chip. Secondary ions emitted from the back side as the aperture is being formed are detected by a detection device and used by a controller adapted to control the substrate removal arrangement as a function of the detected secondary ion emission.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.